# Faulty LimeSDR? (Self-test failed)

**URL:** <https://discourse.myriadrf.org/t/faulty-limesdr-self-test-failed/5301>\
**Category:** LimeSDR\
**Created:** [26 October 2019 11:06 UTC](https://discourse.myriadrf.org/t/faulty-limesdr-self-test-failed/5301 "2019-10-26T11:06:42Z")\
**Posts on this page:** 2\
**Page:** 1

<div class="post-metadata">

**Author:** ![perillamint](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/perillamint/32/3108_2.png) [@perillamint](https://discourse.myriadrf.org/u/perillamint)\
**Post date:** [26 October 2019 11:06 UTC](https://discourse.myriadrf.org/t/faulty-limesdr-self-test-failed/5301/1 "2019-10-26T11:06:42Z")

</div>

Hello, I just upgraded my LimeSuite to 19.04 and I just ran a self test.

It says

```auto
[perillamint@deepthought ~]$ LimeQuickTest 
[TESTING STARTED]
->Start time: Sat Oct 26 19:44:25 2019

->Device: LimeSDR-USB, media=USB 3.0, module=FX3, addr=1d50:6108, serial=0009062000C41A1A
  Serial Number: 0009062000C41A1A

[Clock Network Test]
->FX3 GPIF clock test
  Test results: 29801; 33557; 37313 - PASSED
->Si5351C test
  CLK0: 17554 / 17554 - PASSED
  CLK1: 17554 / 17554 - PASSED
  CLK2: 17554 / 17554 - PASSED
  CLK3: 17554 / 17554 - PASSED
  CLK4: 17554 / 17554 - PASSED
  CLK5: 17554 / 17554 - PASSED
  CLK6: 17554 / 17554 - PASSED
->ADF4002 Test
  Result: 10 - PASSED
->VCTCXO test
  Results : 5112976 (min); 5113092 (max) - PASSED
->Clock Network Test PASSED

[FPGA EEPROM Test]
->Read EEPROM
->Read data: 11 05 0F 11 05 0F 02
->FPGA EEPROM Test PASSED

[LMS7002M Test]
->Perform Registers Test
->External Reset line test
  Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
  Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED

[RF Loopback Test]
Note: The test should be run without anything connected to RF ports
->Configure LMS
->Run Tests (TX_2-> LNA_L):
  CH0 (SXR=800.0MHz, SXT=805.0MHz): Result:(-13.8 dBFS, 5.00 MHz) - PASSED
  CH1 (SXR=800.0MHz, SXT=805.0MHz): Result:(-16.0 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_W):
  CH0 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-13.7 dBFS, 5.00 MHz) - PASSED
  CH1 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-17.3 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_2-> LNA_H):
  CH0 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-15.8 dBFS, 5.00 MHz) - PASSED
  CH1 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-29.1 dBFS, 5.00 MHz) - FAILED
->RF Loopback Test FAILED

=> Board tests FAILED <=

Elapsed time: 1.43 seconds

```

Is my LimeSDR faulty? Ofc, I didn’t connected anything to RF input/output port during test.

---

<div class="post-metadata">

**Author:** ![IgnasJ](https://avatars.discourse-cdn.com/v4/letter/i/278dde/32.png) [@IgnasJ](https://discourse.myriadrf.org/u/IgnasJ)\
**Post date:** [28 October 2019 10:25 UTC](https://discourse.myriadrf.org/t/faulty-limesdr-self-test-failed/5301/2 "2019-10-28T10:25:20Z")

</div>

Signal level on TX2\_2 to RX2\_H path is lower than it should be (as you can see comparing it to other results). It is likely that there is something wrong with RX2\_H path on your board. TX2\_2 port is also tested in TX\_2-\>LNA\_L test and that is OK.