# Failing RF Loopback Test -Any Advice?

**URL:** <https://discourse.myriadrf.org/t/failing-rf-loopback-test-any-advice/7138>\
**Category:** LimeSDR\
**Created:** [20 May 2021 19:34 UTC](https://discourse.myriadrf.org/t/failing-rf-loopback-test-any-advice/7138 "2021-05-20T19:34:37Z")\
**Posts on this page:** 7\
**Page:** 1

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**Author:** ![killick](https://avatars.discourse-cdn.com/v4/letter/k/c5a1d2/32.png) [@killick](https://discourse.myriadrf.org/u/killick)\
**Post date:** [20 May 2021 19:34 UTC](https://discourse.myriadrf.org/t/failing-rf-loopback-test-any-advice/7138/1 "2021-05-20T19:34:37Z")

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[TESTING STARTED]  
-\>Start time: Thu May 20 16:54:29 2021  
-\>LimeSuite version: 20.10.0-g1480bfea  
-\>Device: LimeSDR-USB, media=USB 3.0, module=FX3, serial=0009072C02882F32, index=0, HW=4, GW=2.23  
Serial Number: 0009072C02882F32  
Chip temperature: 48 C  
[Clock Network Test]  
-\>FX3 GPIF clock test  
Test results: 25554; 29310; 33066 - PASSED  
-\>Si5351C test  
CLK0: 17554 / 17554 - PASSED  
CLK1: 17554 / 17554 - PASSED  
CLK2: 17554 / 17554 - PASSED  
CLK3: 17554 / 17554 - PASSED  
CLK4: 17554 / 17554 - PASSED  
CLK5: 17554 / 17554 - PASSED  
CLK6: 17554 / 17554 - PASSED  
-\>ADF4002 Test  
Result: 10 - PASSED  
-\>VCTCXO test  
Results : 5112983 (min); 5113115 (max) - PASSED  
-\>Clock Network Test PASSED  
[FPGA EEPROM Test]  
-\>Read EEPROM  
-\>Read data: 12 08 02 12 08 02 02  
-\>FPGA EEPROM Test PASSED  
[LMS7002M Test]  
-\>Perform Registers Test  
-\>External Reset line test  
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD  
Reg 0x20: value after reset 0x0FFFF  
-\>LMS7002M Test PASSED  
[RF Loopback Test]  
Note: The test should be run without anything connected to RF ports  
-\>Configure LMS  
SetPllFrequency: error configuring phase  
SetPllFrequency: error configuring phase  
SetPllFrequency: error configuring phase  
SetPllFrequency: error configuring phase  
SetPllFrequency: error configuring phase  
SetPllFrequency: error configuring phase  
SetPllFrequency: error configuring phase  
SetPllFrequency: error configuring phase  
SetPllFrequency: error configuring phase  
SetPllFrequency: error configuring phase  
LML TX phase search FAIL  
Failed to set sample rate  
-\>RF Loopback Test FAILED  
=\> Board tests FAILED \<=  
Elapsed time: 3.63 seconds

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**Author:** ![yt7pwr](https://avatars.discourse-cdn.com/v4/letter/y/ecd19e/32.png) [@yt7pwr](https://discourse.myriadrf.org/u/yt7pwr)\
**Post date:** [20 May 2021 20:27 UTC](https://discourse.myriadrf.org/t/failing-rf-loopback-test-any-advice/7138/2 "2021-05-20T20:27:18Z")

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First try to lower chip temperature (currently is 48C).

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**Author:** ![killick](https://avatars.discourse-cdn.com/v4/letter/k/c5a1d2/32.png) [@killick](https://discourse.myriadrf.org/u/killick)\
**Post date:** [20 May 2021 20:49 UTC](https://discourse.myriadrf.org/t/failing-rf-loopback-test-any-advice/7138/3 "2021-05-20T20:49:26Z")

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Ok, thanks for the help, I will try that out.

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**Author:** ![killick](https://avatars.discourse-cdn.com/v4/letter/k/c5a1d2/32.png) [@killick](https://discourse.myriadrf.org/u/killick)\
**Post date:** [21 May 2021 13:11 UTC](https://discourse.myriadrf.org/t/failing-rf-loopback-test-any-advice/7138/4 "2021-05-21T13:11:01Z")

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I let the board cool for an hour and ran the test again but, even though its cool the reading still says chip temperature is 46C and I get the same output as before. Could this temperature reading be due to some hardware or software issue?

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**Author:** ![andrewback](https://avatars.discourse-cdn.com/v4/letter/a/22d042/32.png) [@andrewback](https://discourse.myriadrf.org/u/andrewback)\
**Post date:** [22 May 2021 10:25 UTC](https://discourse.myriadrf.org/t/failing-rf-loopback-test-any-advice/7138/5 "2021-05-22T10:25:36Z")

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Tagging @Zack.

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**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [27 May 2021 07:04 UTC](https://discourse.myriadrf.org/t/failing-rf-loopback-test-any-advice/7138/6 "2021-05-27T07:04:09Z")

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> [@killick](#):
>
> SetPllFrequency: error configuring phase

This tells that there is IQ data interface problem between FPGA and LMS7002M. Contact the seller for RMA.

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**Author:** ![killick](https://avatars.discourse-cdn.com/v4/letter/k/c5a1d2/32.png) [@killick](https://discourse.myriadrf.org/u/killick)\
**Post date:** [27 May 2021 22:04 UTC](https://discourse.myriadrf.org/t/failing-rf-loopback-test-any-advice/7138/7 "2021-05-27T22:04:50Z")

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Ok, thanks