# Dual XTRX Deterministic Coherent Operation
**URL:** https://discourse.myriadrf.org/t/dual-xtrx-deterministic-coherent-operation/13063
**Category:** General Discussion
**Created:** [3 March 2026 11:52 UTC](https://discourse.myriadrf.org/t/dual-xtrx-deterministic-coherent-operation/13063 "2026-03-03T11:52:59Z")
**Posts on this page:** 6
**Page:** 1
### Author:  [@tfrond](https://discourse.myriadrf.org/u/tfrond)
#### Post date: [3 March 2026 11:53 UTC](https://discourse.myriadrf.org/t/dual-xtrx-deterministic-coherent-operation/13063/1 "2026-03-03T11:53:00Z")
Hello,
We are finalizing a carrier design hosting two XTRX modules (mini-PCIe)
behind a PCIe switch (Orange Pi 5 Ultra host) and intend to operate them
in deterministic phase-coherent mode.
Synchronization architecture:
- u-blox ZED-F20P (RTK GNSS) as master timing source
- 10 MHz reference distributed to both XTRX modules via mini-PCIe pin
19 (MHZ\_IN)
- 1PPS distributed via mini-PCIe pin 3 (1PPSI\_GPIO1)
- Star topology with low-skew clock/PPS fanout buffers
- Matched-length PCB routing to each socket
- 1PPS derived deterministically from the same 10 MHz reference
- No U.FL sync paths; injection exclusively via mini-PCIe pins
Our expectation is that with shared 10 MHz and shared 1PPS, both boards
will: 1) Lock to the common frequency reference, 2) Align epoch
deterministically, 3) Exhibit stable, calibratable phase offsets
suitable for coherent MIMO.
Before freezing hardware, we would like confirmation that:
- 10 MHz on MHZ\_IN is fully supported and recommended for multi-board
coherent operation,
- 1PPS via 1PPSI\_GPIO1 is the correct mechanism for deterministic time
alignment,
- There are no known firmware, driver, or FPGA constraints that would
prevent stable multi-board phase coherence under this architecture.
We’s really appreciate any guidance to coherent multi-XTRX operation.
Thanks,
Tom
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### Author:  [@andrewback](https://discourse.myriadrf.org/u/andrewback)
#### Post date: [6 March 2026 14:14 UTC](https://discourse.myriadrf.org/t/dual-xtrx-deterministic-coherent-operation/13063/2 "2026-03-06T14:14:03Z")
Since this is a mixture of hardware, gateware and software questions, tagging @zack , @VytautasB and @ricardas .
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### Author:  [@tfrond](https://discourse.myriadrf.org/u/tfrond)
#### Post date: [10 March 2026 07:23 UTC](https://discourse.myriadrf.org/t/dual-xtrx-deterministic-coherent-operation/13063/3 "2026-03-10T07:23:14Z")
Apologies for bumping this.
I do need to make some decisions. We can create a disciplined (derived from 1PPS GNSS source) reference clock of a variety of frequencies (from miniature OCXO) suitable for distribution to both XTRX modules. But the biggest question, the elephant in the room as it were, remains, which is point 3 above, namely:
1. Exhibit stable, calibratable phase offsets suitable for coherent MIMO.
Surely there must be a reference example somewhere since the board is marketed as being suitable for scalable solutions?
Thanks.
---
### Author:  [@VytautasB](https://discourse.myriadrf.org/u/VytautasB)
#### Post date: [10 March 2026 08:51 UTC](https://discourse.myriadrf.org/t/dual-xtrx-deterministic-coherent-operation/13063/4 "2026-03-10T08:51:23Z")
Hi @tfrond ,
To clarify the gateware perspective, are you targeting **LimeSDR XTRX v1.3**?
Regarding your architecture:
- **10 MHz referece and mini-PCIe pin19 (PCIE\_CLK\_IN) -** Yes, the gateware allows switching the LMS7002M PLL reference between the internal TCXO and an external source via this pin. While 10 MHz is within LMS7002 supported PLL reference frequency range I would recommend checking and verifying LMS7002 PLL lock range if it suites your needs with 10MHz reference.
- **1PPS via 1PPSI\_GPIO1 -** yes, gateware supports selecting this GPIO to trigger a synchronous reset/alignment of the sample counters across multiple modules. While this architecture ensures the sample counters are aligned but to achieve true Phase Coherence for MIMO, you will likely still need a software-based calibration step.
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### Author:  [@chaloz](https://discourse.myriadrf.org/u/chaloz)
#### Post date: [18 March 2026 10:19 UTC](https://discourse.myriadrf.org/t/dual-xtrx-deterministic-coherent-operation/13063/5 "2026-03-18T10:19:40Z")
I’ve tried to run two LimeSDR XTRXs coherently using GPSDO with two phase aligned outputs: one for clock with 26MHz and one for 1PPS. So I feed these to two XTRXs (through U.FL connectors) and they are pretty much phase aligned on the RX side (I’ve only tested RX), BUT they have initial random phase offset of several samples (my sampling frequency is 12MHz). This seem to change every time the RX stream is started. I’m assuming this has to do with clock domain crossings, but I would have thought that the phase error would be ±1 sample, yet it seems more than that in my case.
Tested on 3.5 GW.
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### Author:  [@spet](https://discourse.myriadrf.org/u/spet)
#### Post date: [12 April 2026 04:24 UTC](https://discourse.myriadrf.org/t/dual-xtrx-deterministic-coherent-operation/13063/6 "2026-04-12T04:24:33Z")
> [@chaloz](#):
>
> I’ve tried to run two LimeSDR XTRXs coherently using GPSDO with two phase aligned outputs: one for clock with 26MHz and one for 1PPS. So I feed these to two XTRXs (through U.FL connectors) and they are pretty much phase aligned on the RX side (I’ve only tested RX), BUT they have initial random phase offset of several samples (my sampling frequency is 12MHz). This seem to change every time the RX stream is started. I’m assuming this has to do with clock domain crossings, but I would have thought that the phase error would be ±1 sample, yet it seems more than that in my case.
i believe you should get constant phase offset across multiple xtrxs, but that phase offset would be random from startup to startup and LO change. both xtrxs are fed a common clock, but that clock runs an independent fractional-n pll on each xtrx and thus causes a different phase from startup-to-startup and LO change, from my understanding
do you have plots of the phase between channels like in this post [Expected phase error when synchronizing multiple xtrxs [phase coherent processing]](https://discourse.myriadrf.org/t/expected-phase-error-when-synchronizing-multiple-xtrxs-phase-coherent-processing/13101) ?