Data flow between LMS7002M and FW/FPGA and how to configure

Hi @rene,


Looks like a nice project!

Yes, a nice challenging project - it is already a lot of fun. So far we are quite pleased with the capability of the LimeSDR - just a little overwhelmed with all the signal processing choices.

On the subject of data transfer:

  1. If I bypass the FPGA, using the code you referenced, can I still read the I and Q data directly from the LMS7 chip? I looked at the LMS7 register map and I could not find the register address from which to read the I and Q data.

  2. I am currently reading I and Q at 30 MB/s through the SoapySDR interface with the standard gateway. Do you know if this means 30 Mega Samples per second where 1 sample is two 12-bit values or does it literally means 30 Mega bytes (8-bit) per second?

Hi @rene,

There is no possibility to read data from LMS7002M via SPI. Well, there is, but it is not synchronized with the clock and dedicated for test purposes only. You have to catch the IQ data with FPGA via digital interface.

It is megabytes per second.

Thanks Zack - that makes sense to get precise timing without jitter.