# Data flow between LMS7002M and FW/FPGA and how to configure

**URL:** <https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501>\
**Category:** LimeSDR\
**Created:** [24 July 2017 10:03 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501 "2017-07-24T10:03:57Z")\
**Posts on this page:** 4\
**Page:** 2

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**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [27 July 2017 07:02 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/21 "2017-07-27T07:02:09Z")

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Hi @rene,

> [@rene](#):
>
> I see. So the code changes you provided re-route the SPI connection that NIOS II was using to the GPIOs.

Correct.

> [@rene](#):
>
> We do have to build a custom gateway because we plan to do some signal processing at the FPGA and then take the resulting data and provide it on demand (so we can use the same spi for commands and data transfer). We are downsampling so the resulting data rate will be 1kHz which I’m assuming should not be an issue to fetch every half second or so.

Looks like a nice project!

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**Author:** ![rene](https://avatars.discourse-cdn.com/v4/letter/r/7cd45c/32.png) [@rene](https://discourse.myriadrf.org/u/rene)\
**Post date:** [27 July 2017 11:44 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/22 "2017-07-27T11:44:12Z")

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Yes, a nice challenging project - it is already a lot of fun. So far we are quite pleased with the capability of the LimeSDR - just a little overwhelmed with all the signal processing choices.

On the subject of data transfer:

1. If I bypass the FPGA, using the code you referenced, can I still read the I and Q data directly from the LMS7 chip? I looked at the LMS7 register map and I could not find the register address from which to read the I and Q data.

2. I am currently reading I and Q at 30 MB/s through the SoapySDR interface with the standard gateway. Do you know if this means 30 Mega Samples per second where 1 sample is two 12-bit values or does it literally means 30 Mega bytes (8-bit) per second?

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**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [27 July 2017 12:24 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/23 "2017-07-27T12:24:16Z")

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Hi @rene,

> [@rene](#):
>
> If I bypass the FPGA, using the code you referenced, can I still read the I and Q data directly from the LMS7 chip? I looked at the LMS7 register map and I could not find the register address from which to read the I and Q data.

There is no possibility to read data from LMS7002M via SPI. Well, there is, but it is not synchronized with the clock and dedicated for test purposes only. You have to catch the IQ data with FPGA via digital interface.

> [@rene](#):
>
> I am currently reading I and Q at 30 MB/s through the SoapySDR interface with the standard gateway. Do you know if this means 30 Mega Samples per second where 1 sample is two 12-bit values or does it literally means 30 Mega bytes (8-bit) per second?

It is megabytes per second.

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<div class="post-metadata">

**Author:** ![rene](https://avatars.discourse-cdn.com/v4/letter/r/7cd45c/32.png) [@rene](https://discourse.myriadrf.org/u/rene)\
**Post date:** [27 July 2017 12:28 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/24 "2017-07-27T12:28:27Z")

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Thanks Zack - that makes sense to get precise timing without jitter.

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