# Data flow between LMS7002M and FW/FPGA and how to configure

**URL:** <https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501>\
**Category:** LimeSDR\
**Created:** [24 July 2017 10:03 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501 "2017-07-24T10:03:57Z")\
**Posts on this page:** 20\
**Page:** 1

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**Author:** ![gchat](https://avatars.discourse-cdn.com/v4/letter/g/ecccb3/32.png) [@gchat](https://discourse.myriadrf.org/u/gchat)\
**Post date:** [24 July 2017 10:03 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/1 "2017-07-24T10:03:57Z")

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Hi,

After looking at the documents, I am unable to find proper answers to my questions. Can someone please help.

1. I understand that LMS7002M chip has MCU connected to it, that has it’s own FW for configuration etc. I can see some Vendor requests to configure MCU\_FW and Boot MCU, but I am curious to know how these requests flow to the MCU and whether there any success/failure response expected?

2. Can someone please point me to particular options in LimeSuite to do the above?

Thanks a lot for your kind attention.  
Regards.

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**Author:** ![andrewback](https://avatars.discourse-cdn.com/v4/letter/a/22d042/32.png) [@andrewback](https://discourse.myriadrf.org/u/andrewback)\
**Post date:** [24 July 2017 13:34 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/2 "2017-07-24T13:34:30Z")

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LMS7002M has an MCU integrated, that by default is used for things such as device calibration. Source is in the Lime Suite GitHub repo:

> **[myriadrf/LimeSuite](https://github.com/myriadrf/LimeSuite/tree/master/mcu_program)**
>
> Driver and GUI for LMS7002M-based SDR platforms. Contribute to myriadrf/LimeSuite development by creating an account on GitHub.

An alternate MCU firmware is used if you run the pyLMS7002M VNA example:

> **[myriadrf/pyLMS7002M](https://github.com/myriadrf/pyLMS7002M/tree/master/examples/VNA/mcu_vna)**
>
> pyLMS7002M Python package. Contribute to myriadrf/pyLMS7002M development by creating an account on GitHub.

I assume this is what you meant, although LMS7002M does have an MCU _connected to it_ also — a NIOS II soft-core in the FPGA, which provides SPI interface.

> **[myriadrf/LimeSDR-USB\_GW](https://github.com/myriadrf/LimeSDR-USB_GW/tree/master/software)**
>
> Altera Cyclone IV FPGA project for the USB 3.0 LimeSDR board - myriadrf/LimeSDR-USB\_GW

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<div class="post-metadata">

**Author:** ![gchat](https://avatars.discourse-cdn.com/v4/letter/g/ecccb3/32.png) [@gchat](https://discourse.myriadrf.org/u/gchat)\
**Post date:** [25 July 2017 08:46 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/3 "2017-07-25T08:46:23Z")

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@andrewback, Thanks a lot for your response.

> [@andrewback](#):
>
> I assume this is what you meant, although LMS7002M does have an MCU connected to it also — a NIOS II soft-core in the FPGA, which provides SPI interface.

Ok. So the complete data flow should be like this?:  
Vendor Request from Host PC → FX3 → Pass on to I2C-SPI Bridge → FPGA NIOS-II soft core passes the same data as it is to LMS7002M over SPI → MCU handles this data/request and performs the action  
Is this correct?

I am confused with so much code with name _mcu_. Is there any method to control/interact with MCU directly (without going through FW/FPGA)?  
Also, can you please help me with the options to perform MCU related actions from LimeSuite GUI.

Thanks a lot.  
Gaurav

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**Author:** ![andrewback](https://avatars.discourse-cdn.com/v4/letter/a/22d042/32.png) [@andrewback](https://discourse.myriadrf.org/u/andrewback)\
**Post date:** [25 July 2017 09:37 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/4 "2017-07-25T09:37:40Z")

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> [@gchat](#):
>
> Pass on to I2C-SPI Bridge

I don’t believe that an I2C-SPI bridge is used any more and think this was just prior to there being NIOS-II in the FPGA, which now instead provides USB-\>SPI interface (GPIF II on FX3 to FPGA for control and samples).

@Zack, perhaps you could confirm and comment on the other questions?

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**Author:** ![gchat](https://avatars.discourse-cdn.com/v4/letter/g/ecccb3/32.png) [@gchat](https://discourse.myriadrf.org/u/gchat)\
**Post date:** [25 July 2017 09:41 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/5 "2017-07-25T09:41:42Z")

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Oh is it? I can see FX3 code sending over I2C-SPI bridge for all the requests related to FPGA/LMS7002M and handling nothing else after that. I think it’s definitely using I2C-SPI bridge to send requests to FPGA.  
Thanks for your response.

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**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [25 July 2017 11:26 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/6 "2017-07-25T11:26:34Z")

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Hi @gchat,

Initially many on-board peripherals were controlled using I2C SPI bridge. Then we moved this task to NIOS CPU (as @andrewback rightly mentioned) and control commands from the PC are sent to different endpoints. Hence control functionality is still in the FX3, but it is not used.

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**Author:** ![gchat](https://avatars.discourse-cdn.com/v4/letter/g/ecccb3/32.png) [@gchat](https://discourse.myriadrf.org/u/gchat)\
**Post date:** [25 July 2017 11:33 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/7 "2017-07-25T11:33:09Z")

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Oh Ok @Zack. Thanks for that.  
So, are they alternates to each other. I mean I can either use I2C-SPI Bridge or NIOS-II for controlling the peripherals??  
Using the bridge would make it easier in terms of Host PC sending all requests to the same endpoint, right? But what is the use of NIOS in that case? Only providing SPI from FPGA to LMS7002M or something else?

In other case of using NIOS for these tasks instead of I2C-SPI Bridge, can you please point me to any manual or document describing the control/data flow.

Thanks a lot @Zack and @andrewback for the help so far. Regards.

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**Author:** ![andrewback](https://avatars.discourse-cdn.com/v4/letter/a/22d042/32.png) [@andrewback](https://discourse.myriadrf.org/u/andrewback)\
**Post date:** [25 July 2017 11:39 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/8 "2017-07-25T11:39:29Z")

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SPI going via FX3 parallel interface -\> FPGA NIOS -\> LMS7002M is much faster than when the route is from FX3 I2C via bridge and on to LMS7002M. I2C provides a bottleneck in the latter.

We will only officially support the current mechanism using NIOS-II for SPI, but given it’s open source, you are free to modify the host and FX3 code, FPGA RTL and NIOS-II firmware as you please 🙂

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**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [25 July 2017 11:44 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/9 "2017-07-25T11:44:14Z")

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We use FX3 modification with 32 bit GPIF data interface to FPGA. There is FX3 flavor with 16 bit GPIF interface, but data throughput is two times less than in 32 bit case. But there is no native SPI interface in 32 bit GPIF flavor. Hence initially we decided to use I2C to SPI bridge, while native I2C is sill there. But the issue was that it slows down the control communication. To overcome this we implemented NIOS for this task.

> [@gchat](#):
>
> Using the bridge would make it easier in terms of Host PC sending all requests to the same endpoint, right?

No difference from software point of view.

> [@gchat](#):
>
> But what is the use of NIOS in that case? Only providing SPI from FPGA to LMS7002M or something else?

Mainly to control all the on-board peripherals. NIOS doesn’t have an access to IQ data.

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<div class="post-metadata">

**Author:** ![gchat](https://avatars.discourse-cdn.com/v4/letter/g/ecccb3/32.png) [@gchat](https://discourse.myriadrf.org/u/gchat)\
**Post date:** [25 July 2017 11:45 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/10 "2017-07-25T11:45:59Z")

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> [@andrewback](#):
>
> SPI going via FX3 parallel interface -\> FPGA NIOS -\> LMS7002M

Can you please help me find the code in FX3 for this. Which requests are supported using this mechanism. That would be a great help. Also, how would SPI be used if 32-bit GPIF is used?  
Thanks

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<div class="post-metadata">

**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [25 July 2017 11:49 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/11 "2017-07-25T11:49:42Z")

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> [@gchat](#):
>
> Can you please help me find the code in FX3 for this.

There is no FX3 code involved in this task at all. The control packets from PC are just re-transmitted to GPIF interface where NIOS catches it.

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**Author:** ![gchat](https://avatars.discourse-cdn.com/v4/letter/g/ecccb3/32.png) [@gchat](https://discourse.myriadrf.org/u/gchat)\
**Post date:** [25 July 2017 11:56 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/12 "2017-07-25T11:56:04Z")

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> [@Zack](#):
>
> There is no FX3 code involved in this task at all.

Ok thanks. So it’s only coded in FPGA and NIOS IP code?

In that case, is the FX3 code using: I2C\_Addr = I2C\_ADDR\_SC18IS602B; and CyU3PI2cTransmitBytes () obsolete  
for requests like CMD\_LMS7002\_WR, CMD\_LMS7002\_RD, CMD\_BRDSPI16\_WR, CMD\_LMS\_MCU\_FW\_WR etc.?

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**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [25 July 2017 12:02 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/13 "2017-07-25T12:02:29Z")

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> [@gchat](#):
>
> So it’s only coded in FPGA and NIOS IP code?

Well, there is FX3 code involved in endpoint setup only. And after that PC and NIOS are involved.[quote=“gchat, post:12, topic:1501”]  
In that case, is the FX3 code using: I2C\_Addr = I2C\_ADDR\_SC18IS602B; and CyU3PI2cTransmitBytes () obsolete  
for requests like CMD\_LMS7002\_WR, CMD\_LMS7002\_RD, CMD\_BRDSPI16\_WR, CMD\_LMS\_MCU\_FW\_WR etc.?  
[/quote]

Correct. I just would not say it is obsolete. It is just reserved for other tasks, but officially not supported.

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**Author:** ![gchat](https://avatars.discourse-cdn.com/v4/letter/g/ecccb3/32.png) [@gchat](https://discourse.myriadrf.org/u/gchat)\
**Post date:** [25 July 2017 13:21 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/14 "2017-07-25T13:21:06Z")

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Great. Thanks for letting me know. But is there any document giving some details about these changes. Because from the first look at code, I don’t think anybody would figure out that these things are not used.  
So, in short GPIF is being used for everything between FW and FPGA: Controlling Peripherals and Data transfer both.  
And between FPGA, it’s SPI for control and Port1 & Port2 data lines for data. Correct? And all the control part is handled by NIOS?

I will study more and will have many more questions now 🙂  
Regards

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**Author:** ![gchat](https://avatars.discourse-cdn.com/v4/letter/g/ecccb3/32.png) [@gchat](https://discourse.myriadrf.org/u/gchat)\
**Post date:** [26 July 2017 11:26 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/15 "2017-07-26T11:26:44Z")

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> [@Zack](#):
>
> There is no FX3 code involved in this task at all. The control packets from PC are just re-transmitted to GPIF interface where NIOS catches it.

Can someone please help me with this understanding. Thanks in advance.

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**Author:** ![rene](https://avatars.discourse-cdn.com/v4/letter/r/7cd45c/32.png) [@rene](https://discourse.myriadrf.org/u/rene)\
**Post date:** [26 July 2017 13:22 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/16 "2017-07-26T13:22:59Z")

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Hi, I am also interested in the inner workings of communications.  
I am hoping to be able to be able to bypass the USB completely so that I can hook up a SPI or even a uart to the FPGA through the available GPIO lines. This would allow me to use a bare metal micro to process the I and Q data without the need for the LimeSDR USB driver. I have looked at the LMS7 register map and it is pretty straightforward to read and write to the registers. My plan is to modify the FPGA/NIOS code to map this GPIO-based interface to the SPI going to the LMS7 chip and to also respond to requests for bulk data transfers of the I and Q data.

Does any of this sound possible or is there an easier way to talk to the LimeSDR over SPI rather than USB?

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**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [26 July 2017 13:26 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/17 "2017-07-26T13:26:43Z")

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Hi @rene,

Check this:

> [@Control LimeSDR via SPI using Arduino MCU](https://discourse.myriadrf.org/t/control-limesdr-via-spi-using-arduino-mcu/981/20):
>
> Hello @TegwynTwmfatt, So, promises from my side fulfilled. [Here](https://1drv.ms/u/s!AsTX3WCH_RLCgy3-mzrBqMfMVarp) you will find custom FPGA gateware, connection diagram as well as Arduino example sketch file on how to read/write LMS7002M registers. Note please, that you have to use 5V to 3V3 voltage converters on outputs from Arduino. I’ve used 200 Ohm serial resistors for this purpose. Not very elegant way, but did the job. Tested with Arduino Duemilanove. Let me know if you will have any questions. Now is your turn slight_smile

Here you will find FPGA gateware and Arduino example on how to control LMS7002M chip via external SPI, connected to GPIOs.

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**Author:** ![rene](https://avatars.discourse-cdn.com/v4/letter/r/7cd45c/32.png) [@rene](https://discourse.myriadrf.org/u/rene)\
**Post date:** [26 July 2017 13:52 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/18 "2017-07-26T13:52:36Z")

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Thanks Zack.  
This confirms I can use the GPIO lines as a spi.  
Questions:  
Am I correct to assume that the code changes are in the NIOS II?  
Am I correct to assume that the I and Q data is processed by the FPGA before being streamed out the USB and if so, do you have any ideas on how to access the stream without the USB? For example, could one add code to the NIOS II to pre-process the I and Q data and then send it out the GPIO/SPI that is being used also for register read/writes?

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<div class="post-metadata">

**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [26 July 2017 14:07 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/19 "2017-07-26T14:07:49Z")

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Hi @rene,

> [@rene](#):
>
> Am I correct to assume that the code changes are in the NIOS II?

You are not. In the link I just shared, LMS7002M SPI lines are routed to LimeSDR-USB board GPIOs. You need an external SPI master like Arduino in this case, to be able to control LMS7002M. NIOS now doesn’t have an access to LMS7002M SPI.

> [@rene](#):
>
> Am I correct to assume that the I and Q data is processed by the FPGA before being streamed out the USB

Correct. But processing is just packet for USB construction.[quote=“rene, post:18, topic:1501”]  
if so, do you have any ideas on how to access the stream without the USB? For example, could one add code to the NIOS II to pre-process the I and Q data and then send it out the GPIO/SPI that is being used  
[/quote]

Well, you may write IQ samples to the RAM, then process it and then send the data via SPI (means slowly) to the outside world. But this should be a custom gateware.

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<div class="post-metadata">

**Author:** ![rene](https://avatars.discourse-cdn.com/v4/letter/r/7cd45c/32.png) [@rene](https://discourse.myriadrf.org/u/rene)\
**Post date:** [26 July 2017 14:23 UTC](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501/20 "2017-07-26T14:23:57Z")

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I see. So the code changes you provided re-route the SPI connection that NIOS II was using to the GPIOs.  
We do have to build a custom gateway because we plan to do some signal processing at the FPGA and then take the resulting data and provide it on demand (so we can use the same spi for commands and data transfer). We are downsampling so the resulting data rate will be 1kHz which I’m assuming should not be an issue to fetch every half second or so.

[Next page](https://discourse.myriadrf.org/t/data-flow-between-lms7002m-and-fw-fpga-and-how-to-configure/1501.md?page=2)