Case dimensions? RF switching time? Bandwidth>60MHz?

[IgnasJ]

@mzs

The reliance on an external xillybus FPGA code to provide the PCIe interface layer limits throughput to ~200 MB/s each direction which is comparable with USB 3.0 at 400 MB/s in total.

Xiillybus FPGA code limits throughput to 400 MB/s per direction (Cyclone IV PCIe x4, Download Xillybus for PCIe | xillybus.com). When using TX and RX the maximum what I am able to get in LimeSuite on LimeSDR-PCIE is ~370 MB/s in each direction. On LimeSDR-USB it is ~180-190 MB/s in each direction.