Additional features on FPGA

Projects LimeSDR
2

Hello, Martin_T

Not sure if I correctly understand what are you trying to achieve but if you modify your code as:

process(clk, reset_n)
begin
	if reset_n = '0' then 
        mux_sel = '0'
	elsif (clk'event AND clk='1') then 
		if (((abs_val >= threshold OR abs_val_a >= threshold OR abs_val_b >= threshold) AND trigger_en = '1') OR trigger_en = '0') then
            mux_sel = '1';
        else
            mux_sel = mux_sel;
		end if;
	end if;
end process;


process(clk, reset_n)
begin
	if reset_n = '0' then 
		out_wrreq <= '0';
		out_cnt_en <= '0';
	elsif (clk'event AND clk='1') then 
		if mux_sel = '1' then
			out_wrreq <= wrreq;
			out_cnt_en <= in_cnt_en;
		else
            out_wrreq <= '0';
            out_cnt_en <= '0';
		end if;
	end if;
end process;

this will start capturing samples after “abs_val” reaches “threshold” and stop only when reset_n goes to ‘0’.

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