Additional features on FPGA

#1

Hi everybody,
currently I’m working on the implementation of some additional features on the FPGA. First, I created an interface between LimeSDR and Matlab that allows me to manually configure the transceiver chip and the FPGA board with the Matlab software so I can then analyze and visualize the received data.
One of these features on the FPGA should be a single-shot trigger, which should start the transmission of the signal at a certain threshold.
Generally this block is located after the diq2fifo_inst0 object. The transmission is started and stopped with the signals “wrreq” and “cnt_en”.
My problem is that I can’t start the transmission after the signal reaches the threshold and let it continue. As soon as the signal falls below the threshold again, the transmission is also stopped. This causes me to lose a lot of samples during transmission.
The threshold itself is written to an FPGA configuration register via an additional field in the customized LimeSuite GUI or via Matlab and then read in the FPGA.
Maybe someone can give me some tips on how to implement the single-shot trigger correctly. Are the above signals correct to start and stop the streaming function?
The following VHDL code describes the trigger functionality:

process(clk, reset_n)
begin
	if reset_n = '0' then 
		out_wrreq <= '0';
		out_cnt_en <= '0';
	elsif (clk'event AND clk='1') then 
		if (((abs_val >= threshold OR abs_val_a >= threshold OR abs_val_b >= threshold) AND trigger_en = '1') OR trigger_en = '0') then
			out_wrreq <= wrreq;
			out_cnt_en <= in_cnt_en;
		else
			out_wrreq <= '0';
			out_cnt_en <= '0';
		end if;
	end if;
end process;

The abs_val’s are calculated in an additional process…

Thanks in advance for your help
best regards
Martin

#2

Hello, Martin_T

Not sure if I correctly understand what are you trying to achieve but if you modify your code as:

process(clk, reset_n)
begin
	if reset_n = '0' then 
        mux_sel = '0'
	elsif (clk'event AND clk='1') then 
		if (((abs_val >= threshold OR abs_val_a >= threshold OR abs_val_b >= threshold) AND trigger_en = '1') OR trigger_en = '0') then
            mux_sel = '1';
        else
            mux_sel = mux_sel;
		end if;
	end if;
end process;


process(clk, reset_n)
begin
	if reset_n = '0' then 
		out_wrreq <= '0';
		out_cnt_en <= '0';
	elsif (clk'event AND clk='1') then 
		if mux_sel = '1' then
			out_wrreq <= wrreq;
			out_cnt_en <= in_cnt_en;
		else
            out_wrreq <= '0';
            out_cnt_en <= '0';
		end if;
	end if;
end process;

this will start capturing samples after “abs_val” reaches “threshold” and stop only when reset_n goes to ‘0’.

1 Like
#3

Hello, @VytautasB

thank you very much for your quick response. I’ve tried your modified code and it works perfectly. Great work.
Yours sincerely
Martin